Sequential Equivalence Checking for Clock-Gated Circuits

نویسندگان
چکیده

برای دانلود باید عضویت طلایی داشته باشید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Equivalence-checking for Reversible Circuits

Reversible circuits arise in bottlenecks of quantum algorithms, such as Shor’s and Grover’s. More generally, they offer a way to embed an arbitrary conventional computation into the quantum domain, where it can be performed on multiple input combinations at once. Performance optimizations modify reversible circuits for speed, depth and to abide by physical constraints, e.g., of spin-chain archi...

متن کامل

Equivalence Checking of Dissimilar Circuits

We introduce the notion of a Common Specification of circuits that generalizes the current notion of structural similarity. A CS S of circuits N1 and N2 is a circuit of multi-valued blocks from which N1 and N2 can be produced by binary encoding. We show that the equivalence checking of N1,N2 in general resolution (which a non-deterministic proof system) is linear in the number of blocks in S. H...

متن کامل

Using Speculation for Sequential Equivalence Checking

An improved method for speculative reduction is proposed and applied to (suspected) hard verification problems. Several variations of the algorithm were tested: (a) applying speculation initially to the original problem; (b) applying speculation after simplification, before our regular model checker, super_prove is applied, as well as (c) using different filters to reduce the number of speculat...

متن کامل

Verification and Synthesis of Clock-Gated Circuits

Verification and Synthesis of Clock-Gated Circuits by Yu-Yun Dai Doctor of Philosophy in Engineering-Electrical Engineering and Computer Sciences University of California, Berkeley Professor Robert K. Brayton, Chair As system complexity and transistor density increase, the power consumed by digital integrated circuits has become a critical constraint for VLSI design and manufacturing. To reduce...

متن کامل

Low Power Clock Gated Sequential Circuit Design

Reducing Power dissipation is one of the crucial problems in today’s scenario. So this dissipation has become a bottleneck in the design of high speed synchronous systems which are operating at high frequency. Clock signals have been a great source of Power. Design can be made on the basis of Clock gating approach to reduce the consumption of clock’s signal switching power which is the foremost...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

ژورنال

عنوان ژورنال: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

سال: 2014

ISSN: 0278-0070,1937-4151

DOI: 10.1109/tcad.2013.2284190